To meet the demand for miniaturization of form factors and high performance integration, electronic packaging technologies have provided multiple packaging solutions. One electronic packaging solution is solder on die (SOD) with solder paste printing (SPP). For example, SOD may be used with a SPP process in an embedded multi-die interconnect packaging technology. The SOD with SPP process enables a tall solder height for fine pitch interconnects. SOD with SPP, however, requires multiple paste printings and reflows. Disadvantages of multiple reflows are increased resist cross-linking that adversely impacts the photoresist stripability, increased flux interaction with photoresist that leads to flux absorption by the photoresist, and increased post strip photoresist residue and/or missing solder.
Another disadvantage of SOD with SPP occurs during chip (or die) attach using thermal compression bonding (TCB). A major problem encountered during TCB of SOD dies is the inconsistent wicking of solder on copper posts, which may lead to merged solder bumps (bridging) and non-contact opens. One common type of packaging solution that is used to reduce inconsistent wicking during TCB is solder volume reduction. A disadvantage, however, of this solder volume reduction is that it results in smaller chip gaps for underfills.
An additional problem of SOD with traditional solder pastes is enabling bond on trace (BOT). The packaging solution of current solder metallurgy for BOT can result in an uncontrolled spreading of solder that leads to bump bridging and smaller chip gaps.